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EL4581
Data Sheet February 8, 2008 FN7172.1
Sync Separator, 50% Slice, S-H, Filter
The EL4581 extracts timing information from standard negative going video sync found in NTSC, PAL and SECAM broadcast systems. It can also be used in non standard formats and with computer graphics systems at higher scan rates, by adjusting a single external resistor. When the input does not have correct serration pulses in the vertical interval, a default vertical output is produced. Outputs are composite sync, vertical sync, burst/back porch output, and odd/even output. The later operates only in interlaced scan formats. The EL4581 provides a reliable method of determining correct sync slide level by setting it to the mid-point between sync tip and blanking level at the back porch. This 50% level is determined by two internal self timing sample and hold circuits that track sync tip and back porch levels. This also provides a degree of hum and noise rejection to the input signal, and compensates for varying input levels of 0.5VP-P to 2.0VP-P. A built in linear phase, third order, low pass filter attenuates the chroma signal in color systems to prevent incorrectly set color burst from disturbing the 50% sync slide. This device may be used to replace the industry standard LM1881, offering improved performance and reduced power consumption. The EL4581 video sync separator is manufactured using Elantec's high performance analog CMOS process.
Features
* NTSC, PAL and SECAM sync separation * Single supply, +5V * Precision 50% slicing, internal caps * Built-in color burst filter * Decodes non-standard verticals * Pin compatible with LM1881 * Low power * Typically 1.5mA supply current * Resistor programmable scan rate * Few external components * Available in 8 Ld PDIP and SOIC packages * Pb-free available (RoHS compliant)
Applications
* Video special effects * Video test equipment * Video distribution * Displays * Imaging * Video data capture * Video triggers
Ordering Information Pinout
EL4581 (8 LD SOIC, PDIP) TOP VIEW
COMPOSITE SYNC OUT COMPOSITE VIDEO IN VERTICAL SYNC OUT GND 1 2 3 4 8 7 6 5 VDD 5V ODD/EVEN OUTPUT RSET BURST/BACK PORCH OUTPUT
PART NUMBER EL4581CN EL4581CS*
PART MARKING EL4581CN 4581CS
TEMP. RANGE
PACKAGE
PKG. DWG. # MDP0031 MDP0027 MDP0027
-40C to +85C 8 Ld PDIP -40C to +85C 8 Ld SOIC -40C to +85C 8 Ld SOIC (Pb-free)
EL4581CSZ* 4581CSZ (Note)
*Add "-T7" or "-T13" suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Demo Board
A dedicated demo board is not available. However, this device can be placed on the EL4584/5 Demo Board.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2003, 2008. All Rights Reserved. Elantec is a registered trademark of Elantec Semiconductor, Inc. All other trademarks mentioned are the property of their respective owners. Manufactured under U.S. Patent 5,528,303. Manufactured under License, U.S. Patents 5,486,869; 5,754,250.
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EL4581
Absolute Maximum Ratings (TA = +25C)
VCC Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7V Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Pin Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VCC +0.5V
Thermal Information
Maximum Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . See Curves Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . . . +150C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Operating Temperature Range . . . . . . . . . . . . . . . . .-40C to +85C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
DC Electrical Specifications
PARAMETER IDD Clamp Voltage Discharge Current Clamp Charge Current Ref Voltage VOL Output Low Voltage VOH Output High Voltage
Unless otherwise stated, VDD = 5V, TA = +25C, RSET = 680k. DESCRIPTION TEMP (C) +25 +25 +25 +25 +25 +25 +25 +25 4 2.4 MIN (Note 7) 0.75 1.3 6 2 1.5 TYP 1.7 1.5 10 3 1.8 2.1 800 MAX (Note 7) 3 1.9 20 UNIT mA V A mA V mV V V
VDD = 5V (Note 1) Pin 2, Unloaded Pin 2 = 2V Pin 2, VIN = 1V Pin 6, VDD = 5V (Note 2) IOL = 1.6mA IOH = -40A IOH = -1.6mA
NOTES: 1. No video signal, outputs unloaded. 2. Tested for VDD 5V 5%.
Dynamic Specifications
PARAMETER Vertical Sync Width, tVS Burst/Back Porch Width, tB Vertical Sync Default Delay tVSD Filter Attenuation Composite Sync Prop Delay Input Dynamic Range Slice Level
VDD = 5V, IVP-P video, TA = +25C, CL = 15pF, IOH = -1.6mA, IOL = 1.6mA. Signal voltages are peak to peak. DESCRIPTION (Note 3) (Note 3) TEMP (C) +25 +25 +25 FIN = 3.4MHz (Note 4) VIN- Composite Sync (Note 3) Peak-to-Peak NTSC Signal (Note 5) Input Voltage = 1VP-P (Note 6) +25 +25 +25 +25 Full 0.5 40 40 50 50 MIN (Note 7) 190 2.5 40 TYP 230 3.5 55 24 260 400 2 60 60 MAX (Note 7) 300 4.5 70 UNIT s s s dB ns V % %
NOTES: 3. C/S, Vertical and Burst outputs are all active low (VOH = 2.4V, VOL = 0.8V). 4. Attenuation is a function of RSET (PIN 6). 5. Typical min is 0.3VP-P. 6. Refers to threshold level of sync tip to back porch amplitude. 7. Parts are 100% tested at +25C. Over-temperature limits established by characterization and are not production tested.
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FN7172.1 February 8, 2008
EL4581 Pin Descriptions
PIN NUMBER 1 2 3 4 5 6 7 8 NOTE: 8. RSET must be a 1% resistor. PIN NAME Composite Sync Out Composite Video in Vertical Sync Out GND Burst/Back Porch Output RSET (Note 8) Odd/Even Output VDD 5V FUNCTION Composite sync pulse output. Sync pulses start on a falling edge and end on a rising edge. AC coupled composite video input. Sync tip must be at the lowest potential (Positive picture phase). Vertical sync pulse output. The falling edge of Vert Sync is the start of the vertical period. Supply ground. Burst/Back porch output. Low during burst portion of composite video. An external resistor to ground sets all internal timing. 681k, 1% resistor will provide correct timing for NTSC signals. Odd/Even field output. Low during odd fields, high during even fields. Transitions occur at start of Vert Sync pulse. Positive supply. (5V)
Typical Performance Curves
1000 900 800 700 600 500 400 300 200 100 10 1000 800 RSET (k) 600 400 200 15 20 25 30 35 40 FREQUENCY (kHz) 45 50 0 0 2 4 6 CLAMP TIME (s) 8 10
RSET (k)
FIGURE 1. RSET vs HORIZONTAL FREQUENCY
FIGURE 2. BACK PORCH CLAMP, ON-TIME vs RSET
1000 800 RSET (k) RSET (k) 600 400 200 0 0 100 200 300 400 500
1000 800 600 400 200 0 VERTICAL PULSE WIDTH (s) 0 20 40 60 80 100
DELAY TIME (s)
FIGURE 3. VERTICAL PULSE WIDTH vs RSET
FIGURE 4. VERTICAL DEFAULT DELAY, TIME vs RSET
300 250 200 150 -55
SUPPLY CURRENT (mA)
350 PULSE WIDTH (s)
2.0
1.5
1.0
0.5 -55 -25 5 35 65 95 125
-25
5
35
65
95
125
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 5. VERTICAL PULSE WIDTH vs TEMPERATURE
FIGURE 6. SUPPLY CURRENT vs TEMPERATURE
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FN7172.1 February 8, 2008
EL4581 Typical Performance Curves
PACKAGE POWER DISSIPATION VS AMBIENT TEMPERATURE JEDEC JESD51-7 HIGH EFFECTIVE 2.0 THERMAL CONDUCTIVITY TEST BOARD 1.8 1.6 1.471W 1.4 1.2 1.0 1.136W 0.8 0.6 0.4 0.2 0 0 SO8 JA = 110C/W 25 50 75 85 100 125 AMBIENT TEMPERATURE (C) 150 PDIP8 JA = 85C/W PACKAGE POWER DISSIPATION VS AMBIENT TEMPERATURE JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD
1.8 POWER DISSIPATION (W) 1.6
POWER DISSIPATION (W)
1.4 1.25W 1.2 1.0 0.8 0.6 0.4 0.2 0 0 781mW
PDIP8 JA = 100C/W
SO8 JA = 160C/W 25 50 75 85 100 125 AMBIENT TEMPERATURE (C) 150
FIGURE 7. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
FIGURE 8. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
0 -5 OUTPUT (dB) -10 -15 -20 -25 -30 -35 100k 1M 2M 4M 10M
FREQUENCY (Hz)
FIGURE 9. INPUT SIGNAL = 300mVP-P, EL4581 FILTER CHARACTERISITIC CONSTANT DELAY 240ns
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FN7172.1 February 8, 2008
EL4581 Timing Diagrams
SIGNAL 1a. COMPOSITE VIDEO INPUT, FIELD ONE
1.5s230s FIELD ONE TIME +H VERTICAL BLANKING INTERVAL = 20H -0 (1271s +63.5s ) -0s T1 3H 3H 3H 1 2 3 4 5 6 7 8 9 10 19 20 21
H SYNC INTERVAL H
START OF H FIELD ONE PRE-EQUALIZING PULSE INTERVAL
H VERTICAL SYNC PULSE INTERVAL 9 LINE VERTICAL INTERVAL
0.5H POST-EQUALIZING PULSE INTERVAL
H REF SUBCARRIER PHASE, COLOR FIELD ONE
(*SEE NOTE)
SIGNAL 1b. COMPOSITE SYNC OUTPUT, PIN 1
SIGNAL 1c. VERTICAL SYNC OUTPUT, PIN 3
SIGNAL 1d. ODD-EVEN OUTPUT, PIN 7
SIGNAL 1e. BACK PORCH OUTPUT, PIN 5
SEE FIG 2, 3
SEE FIG 4
NOTES: 9. The composite sync output reproduces all the video input sync pulses, with a propagation delay. 10. Vertical sync leading edge is coincident with the first vertical serration pulse leading edge, with a propagation delay. 11. Odd-even output is low for even field, and high for odd field. 12. Back porch goes low for a fixed pulse width on the trailing edge of video input sync pulses. Note that for serration pulses during vertical, the back porch starts on the rising edge of the serration pulse (with propagation delay). FIGURE 10.
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FN7172.1 February 8, 2008
EL4581 Timing Diagrams
(Continued)
SIGNAL 2a. COMPOSITE VIDEO INPUT SLICE LEVEL 50% tCS COMP SYNC PROP DELAY SIGNAL 2b. COMPOSITE SYNC OUTPUT
SIGNAL 2c. VERTICAL SYNC OUTPUT
tCS-VS
COMP SYNC VERT SYNC DELAY
SIGNAL 2d. ODD-EVEN OUTPUT
tCS-OE COMP SYNC ODD/EVEN DELAY
BURST DELAY SIGNAL 2e. BURST/BACK PORCH OUTPUT
tBD tB
BURST WIDTH
FIGURE 11.
SIGNAL 3a. COMPOSITE VIDEO INPUT LINES 2 3 4 5 (NO VERTICAL SYNC PULSES) tVSD SIGNAL 3b. VERTICAL SYNC OUTPUT VERT SYNC DEFAULT DELAY
FIGURE 12.
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FN7172.1 February 8, 2008
EL4581
COLOR BURST 40 IRE INPUT DYNAMIC RANGE 0.5V TO 2V SYNC LEVEL
WHITE LEVEL VIDEO 100 IRE BLACK LEVEL
VSLICE 50% VCLAMP SYNC TIP tCS COMPOSITE SYNC OUTPUT, PIN 1
BLANKING LEVEL
SYNC 40 IRE
DEPENDS ON WIDTH OF INPUT SYNC AT 50% POINTS
BACK PORCH OUTPUT, PIN 5
tB
tBD
FIGURE 13. STANDARD (NTSC INPUT) H. SYNC DETAIL
Description of Operation
A simplified block diagram is shown in Figure 14. The following description is intended to provide the user with sufficient information to be able to understand the effects that the external components and signal conditions have on the outputs of the integrated circuit. The video signal is AC coupled to pin 2 via the capacitor C1, nominally 0.1F. The clamp circuit A1 will prevent the input signal on pin 2 going any more negative than 1.5V, the value of reference voltage VR1. Thus the sync tip, the most negative part of the video waveform, will be clamped at 1.5V. The current source I1, nominally 10A, charges the coupling capacitor during the remaining portion of the H line, approximately 58s for a 15.75kHz timebase. From I*t = C*V, the video time-constant can be calculated. It is important to note that the charge taken from the capacitor during video must be replaced during the sync tip time, which is much shorter, (ratio of x12.5). The corresponding current to restore the charge during sync will therefore be an order of magnitude higher, and any resistance in series with C1 will cause sync tip crushing. For this reason, the internal series resistance has been minimized and external high resistance values in series with the input coupling capacitor should be avoided. The user can exercise some control over the value of the input time constant by introducing an external pull-up resistance from pin 2 to the 5V supply. The maximum voltage across the resistance will be VDD less 1.5V, for black 7
level. For a net discharge current greater than zero, the resistance should be greater than 450k. This will have the effect of increasing the time constant and reducing the degree of picture tilt. The current source I1 directly tracks reference current ITR and thus increases with scan rate adjustment, as explained later. The signal is processed through an active 3-pole filter (F1) designed for minimum ripple with constant phase delay. The filter attenuates the color burst by 24dB and eliminates fast transient spikes without sync crushing. An external filter is not necessary. The filter also amplifies the video signal by 6dB to improve the detection accuracy. Note that the filter cut-off frequency is a function of RSET through IOT and is proportional to IOT. Internal reference voltages (block VREF) with high immunity to supply voltage variation are derived on the chip. Reference VR4 with op amp A2 forces pin 6 to a reference voltage of 1.7V nominal. Consequently, it can be seen that the external resistance RSET will determine the value of the reference current ITR. The internal resistance R3 is only about 6k, much less than RSET. All the internal timing functions on the chip are referenced to ITR and have excellent supply voltage rejection. Comparator C2 on the input to the sample and hold block (S/H) compares the leading and trailing edges of the sync pulse with a threshold voltage VR2, which is referenced at a
FN7172.1 February 8, 2008
EL4581
fixed level above the clamp voltage VR1. The output of C2 initiates the timing one-shots for gating the sample and hold circuits. The sample of the sync tip is delayed by 0.8s to enable the actual sample of 2s to be taken on the optimum section of the sync. pulse tip. The acquisition time of the circuit is about three horizontal lines. The double poly CMOS technology enables long time constants to be achieved with small high quality on-chip capacitors. The back porch voltage is similarly derived from the trailing edge of sync, which also serves to cut off the tip sample if the gate time exceeds the tip period. Note that the sample and hold gating times will track RSET through IOT. The 50% level of the sync tip is derived, through the resistor divider R1 and R2, from the sample and held voltages VTIP and VBP, and applied to the plus input of comparator C1. This comparator has built in hysteresis to avoid false triggering. The output of C2 is a digital 5V signal which feeds the C/S output buffer B1 and the other internal circuit blocks, the vertical, back porch and odd/even functions. The vertical circuit senses the C/S edges and initiates an integrator which is reset by the shorter horizontal sync pulses but times out the longer vertical sync. pulse widths. The internal timing circuits are referenced to IOT and VR3, the time-out period being inversely proportional to the timing current. The vertical output pulse is started on the first serration pulse in the vertical interval and is then self-timed out. In the absence of a serration pulse, an internal timer will default the start of vertical. The back porch is triggered from the sync tip trailing edge and initiates a one-shot pulse. The period of this pulse is again a function of IOT and will therefore track the scan rate set by RSET. The odd/even circuit (O/E) comprises of flip flops which track the relationship of the horizontal pulses to the leading edge of the vertical output, and will switch on every field at the start of vertical. Pin 7 is high during the odd field. Loss of video signal can be detected by monitoring the C/S output. The 50% level of the previous video signal will remain held on the S/H capacitors after the input video signal has gone and the input on pin 2 has defaulted to the clamp voltage. Consequently, the C/S output will remain low longer than the normal vertical pulse period. An external timing circuit could be used to detect this condition.
Block Diagram
1 C SYNC OUT VR1 A1 CLAMP VIDEO IN 2 C1 I1 3-POLE FILTER F1 IOT VBP C2 IOT S/H R1 R2 VTIP IOT D2 VERTICAL DETECT IOT GND 4 BACK PORCH DETECT IOT VR3 VR3 VR1 VR2 VR3 VREF VR4 IREF + A2 ITR C1 + O/E DETECT B4 B1 CS VDD VDD 8
ODD/EVEN OUT 7
VR2
VERTICAL OUT 3
Q1 R3 RSET 6 RSET *NOTE: RSET MUST BE A 1% RESISTOR.
B3
5 BURST/BACK PORCH OUT
FIGURE 14. STANDARD (NTSC INPUT) H. SYNC DETAIL
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FN7172.1 February 8, 2008
EL4581 Small Outline Package Family (SO)
A D N (N/2)+1 h X 45
A E E1 PIN #1 I.D. MARK c SEE DETAIL "X"
1 B
(N/2) L1
0.010 M C A B e C H A2 GAUGE PLANE A1 0.004 C 0.010 M C A B b DETAIL X
SEATING PLANE L 4 4
0.010
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO) INCHES SYMBOL A A1 A2 b c D E E1 e L L1 h N NOTES: 1. Plastic or metal protrusions of 0.006" maximum per side are not included. 2. Plastic interlead protrusions of 0.010" maximum per side are not included. 3. Dimensions "D" and "E1" are measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994 SO-8 0.068 0.006 0.057 0.017 0.009 0.193 0.236 0.154 0.050 0.025 0.041 0.013 8 SO-14 0.068 0.006 0.057 0.017 0.009 0.341 0.236 0.154 0.050 0.025 0.041 0.013 14 SO16 (0.150") 0.068 0.006 0.057 0.017 0.009 0.390 0.236 0.154 0.050 0.025 0.041 0.013 16 SO16 (0.300") (SOL-16) 0.104 0.007 0.092 0.017 0.011 0.406 0.406 0.295 0.050 0.030 0.056 0.020 16 SO20 (SOL-20) 0.104 0.007 0.092 0.017 0.011 0.504 0.406 0.295 0.050 0.030 0.056 0.020 20 SO24 (SOL-24) 0.104 0.007 0.092 0.017 0.011 0.606 0.406 0.295 0.050 0.030 0.056 0.020 24 SO28 (SOL-28) 0.104 0.007 0.092 0.017 0.011 0.704 0.406 0.295 0.050 0.030 0.056 0.020 28 TOLERANCE MAX 0.003 0.002 0.003 0.001 0.004 0.008 0.004 Basic 0.009 Basic Reference Reference NOTES 1, 3 2, 3 Rev. M 2/07
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FN7172.1 February 8, 2008
EL4581 Plastic Dual-In-Line Packages (PDIP)
D E N PIN #1 INDEX
SEATING PLANE L e b
A2
A c
E1
A1 NOTE 5
eA eB
1
2 b2
N/2
MDP0031
PLASTIC DUAL-IN-LINE PACKAGE INCHES SYMBOL A A1 A2 b b2 c D E E1 e eA eB L N NOTES: 1. Plastic or metal protrusions of 0.010" maximum per side are not included. 2. Plastic interlead protrusions of 0.010" maximum per side are not included. 3. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane. 4. Dimension eB is measured with the lead tips unconstrained. 5. 8 and 16 lead packages have half end-leads as shown. PDIP8 0.210 0.015 0.130 0.018 0.060 0.010 0.375 0.310 0.250 0.100 0.300 0.345 0.125 8 PDIP14 0.210 0.015 0.130 0.018 0.060 0.010 0.750 0.310 0.250 0.100 0.300 0.345 0.125 14 PDIP16 0.210 0.015 0.130 0.018 0.060 0.010 0.750 0.310 0.250 0.100 0.300 0.345 0.125 16 PDIP18 0.210 0.015 0.130 0.018 0.060 0.010 0.890 0.310 0.250 0.100 0.300 0.345 0.125 18 PDIP20 0.210 0.015 0.130 0.018 0.060 0.010 1.020 0.310 0.250 0.100 0.300 0.345 0.125 20 TOLERANCE MAX MIN 0.005 0.002 +0.010/-0.015 +0.004/-0.002 0.010 +0.015/-0.010 0.005 Basic Basic 0.025 0.010 Reference Rev. C 2/07 2 1 NOTES
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 10
FN7172.1 February 8, 2008

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